About Me
I am a PhD student in Computer Science and Engineering at UC San Diego, working under Dr. Dean Tullsen. My research focuses on computer architecture security, particularly speculative attacks and mitigations.
I have published papers at top-tier conferences including ASPLOS and DAC, developing novel attacks on modern processors and proposing efficient mitigation strategies. My work bridges hardware and software to address critical security vulnerabilities in modern computing systems.
Key research areas:
- Computer Architecture Security: Speculative attacks, branch prediction vulnerabilities
- Hardware-Software Co-Design: Efficient mitigation frameworks for speculative attacks
- Cache Architecture: Mixed-criticality systems, real-time automotive processors
- Performance Analysis: Gem5 simulation, SPEC benchmarking, overhead optimization
Experience
Advisor: Dr. Dean Tullsen | GPA: 3.95/4.0
Developed a novel speculative attack utilizing the Intel Conditional Branch Predictor to leak complete dynamic control flow of victim functions and poison execution to leak secret values (ASPLOS ‘24).
Currently proposing and designing an efficient and secure architecture-agnostic branch predictor unit for modern server-grade processors.
Recipient of Jacob School of Engineering Fellowship for top PhD applicants.
Advisor: Dr. Trevor Carlson
Proposed a hardware-software co-design framework for efficient and configurable mitigation strategies against speculative attacks, improving performance and efficacy of current and future countermeasures (DAC ‘24).
Built the proposed framework on top of the Gem5 Hardware Simulator for performance and security analysis.
Reduced average performance overhead of state-of-the-art mitigation solutions by 2.7x-3.9x (SPEC’06 Suite).
Hardware Verification and Protocol Development
Developed a Real Time Traffic Generator for TLS 1.2 and 1.3 encryption protocols using Wireshark and Python.
Created Custom Packet Generator for multiple internet protocols using Scapy and TCPDump.
Built verification environment for AES-XTS Encryption Engine using SVerilog and OpenSSL.
Birla Institute of Technology and Science, Pilani
Research Assistant
Jan 2019 – May 2021
https://bits-pilani.ac.in
Advisors: Dr. Pravin Mane and Dr. Biju Raveendran
Project 1: Proposed a 3-Tier Criticality Aware Cache Architecture to increase probability of high criticality tasks meeting worst case execution time in mixed-criticality multi-core real-time automotive systems (IJPEDS ‘23).
Project 2: Designed optimized recursion multiplier achieving 30% delay improvement with <0.01% relative error compared to exact multiplication techniques.
Education
University of California, San Diego
PhD in Computer Science and Engineering
Sep 2023 - Present
Advisor: Dr. Dean Tullsen | GPA: 3.95/4.0
Research Focus: Computer Architecture Security, Speculative Attacks and Mitigations
Recipient of Jacob School of Engineering Fellowship for top PhD applicants.
Key Research Areas: Branch prediction vulnerabilities, hardware-software co-design, performance analysis
Birla Institute of Technology and Science, Pilani
Bachelor of Engineering in Electronics and Communication
Aug 2017 – May 2021
CGPA: 9.65/10 | Top 1% of batch
Graduated with highest honors, maintaining top 1% rank throughout the program.
Recipient of Full Merit Scholarship for all 8 semesters based on academic excellence.
Focus areas: Digital systems, computer architecture, signal processing, and embedded systems.
Publications
Pathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor
ASPLOS '24
2024
H. Yavarzadeh, A. Agarwal, M. Christman, C. Garman, D. Genkin, A. Kwong, D. Moghimi, D. Stefan, M. Taram, D. Tullsen
Developed novel speculative attack exploiting Intel’s conditional branch predictor to leak control flow and secret values.
Levioso: Efficient Compiler-Informed Secure Speculation
DAC '24
2024
A. Hajiabadi, A. Agarwal, A. Diavastos, T. Carlson
Proposed hardware-software co-design framework for configurable mitigation strategies against speculative attacks.
CAMP: A Hierarchical Cache Architecture for Multi-core Mixed Criticality Processors
IJPEDS '23
2023
A. Nair, G. Patil, A. Agarwal, A. Pai, B. Raveendran & S. Punnekkat
Designed 3-tier cache architecture for mixed-criticality real-time automotive systems.
Technical Skills
Programming Languages: C, C++, Python, Assembly, MATLAB, Verilog
Tools & Technologies: Gem5 Simulator, Intel SGX, Wireshark, Cadence Genus Synthesis Solution, Xilinx ISE, Git, OpenSSL, Scapy, TCPDump
Research Expertise: Computer Architecture Security, Speculative Attacks & Mitigations, Cache Architecture Design, Mixed-Criticality Real-Time Systems, Hardware-Software Co-Design, Performance Analysis